In the mobile information terminals including the next generation mobile phone and the mobile PC, improvements of reduction in size, weight and thickness are considered as a key point. For this reason, in order to enhance a competitive power in the technology of the mobile information terminal that is expected to grow highly in future, it is important to develop the high-density packaging technology that is capable of realizing further reduction in size, weight and thickness.
As the high-density packaging technology, there exist a variety of technologies such as flip-chip packaging, multi-chip module, stacked substrate, and so forth. In addition, according to the need to incorporate a plurality of functions into the package, the technological development in the chip size package (CSP) having a structure in which semiconductor chips are stacked is advanced, and further the wafer level CSP using no interposer substrate is developed.
The wafer level CSP has a structure shown in FIG. 1, for example.
In FIG. 1, wirings 102 are formed on a first semiconductor device chip 101, and a second semiconductor device chip 104 is secured to the wirings 102 via solder balls 103. The second semiconductor device chip 104 is smaller in size than the first semiconductor device chip 101.
Also, pin type terminals (vias) 105 are connected to the wirings 102 on the first semiconductor device chip 101 in the peripheral area of the second semiconductor device chip 104. In addition, a sealing resin 106 for sealing the second semiconductor device chip 104 is formed on an upper surface of the first semiconductor device chip 101 to have such a thickness that upper ends of the terminals 105 are exposed from the resin. A solder ball 107 is connected to the upper ends of the terminals 105 respectively.
However, the terminals 105 shown in FIG. 1 are formed on the wirings 102 by the plating method. Thus, it takes much time to form the terminals 105 and thus throughput of the CSP formation is gone down.
Also, forming areas of the terminals 105 are limited to the periphery of the second semiconductor device chip 104. Thus, it is not expected to increase the number of the terminals 105.